1. Field of the Invention
The present invention relates to a chip-on-glass (COG) panel system, and more particularly, to a COG panel system capable of minimizing a block dim effect by considering a relationship among a plurality of chips.
2. Description of the Related Art
In a case where a plurality of chips arrayed on the same printed circuit board (PCB) are operated by using a common power supply, a source of the power supply and pads formed in the chips are connected through metal lines. According to the connection schemes, there are a tape carrier package (TCP) mounting scheme using a tape automated boding (TAB) technique, a chip-on-film (COF) mounting scheme having a flexibility better than that of the TCP mounting scheme, and a chip on glass (COG) mounting scheme using a technique of directly connecting on a glass substrate by using a bump technique. In the COG mounting scheme, films used in the TCP and COF mounting schemes are not used, so that cost can be reduced. However, the COG mounting scheme has a problem in that voltage drop occurs due to specific resistances of signal lines or power supply lines which are constructed with metal lines.
An LCD driver IC (liquid crystal display driver integrated circuit) which is operated in response to a gamma reference voltage applies a data driver signal to an LCD panel. At least two LCD driver ICs are connected to one LCD panel. The gamma reference voltages applied to the LCD driver ICs are varied with the LCD driver ICs. In general, brightness difference among data lines driven by the LCD driver ICs may occur on an LCD screen, which is called a ‘block dim effect. The block dim effect may also occur due to a very small potential difference among the power supply voltage lines connected to the LCD driver ICs. Conventionally, in order to solve the block dim effect, all input resistances of the power supply voltage lines as seen from the LCD driver ICs have been designed to be the same.
FIG. 1 is a view illustrating a configuration of a conventional COG panel system where resistances of power supply voltage lines connected to chips are considered.
Referring to FIG. 1, in the conventional COG panel system 100, two power supply voltage lines VDD_bypass and VDD connected to a flexible printed circuit (FPC) 130 are connected to two chips 110 and 120. The two power supply voltage lines VDD_bypass and VDD have the same voltage level. The bypass power supply voltage line VDD_bypass is connected through a first chip 110 to a second chip 120. The correction power supply voltage line VDD is connected to only the first chip 110.
Since the bypass power supply voltage line VDD_bypass is connected through the first chip 110 to the second chip 120, the input resistance RI2 of the bypass power supply voltage line VDD_bypass as seen from the second chip 120 is a sum of a specific resistance RB1 of the line from the FPC 130 to the first chip 110, an internal specific resistance RB_i of the first chip 110, and a specific resistance RB2 of the line from the first chip 110 to the second chip 120. The input resistance RI2 is expressed by Equation 1.RI2=RB1+RB—i+RB2  [Equation 1]
The input resistance RI1 of the bypass power supply voltage line VDD_bypass as seen from the first chip 110 is only the specific resistance RB1 of the metal line from the FPC 130 to the first chip 110. Therefore, the input resistance RI1 of the bypass power supply voltage line VDD_bypass as seen from the first chip 110 is different from the input resistance RI2 of the bypass power supply voltage line VDD_bypass as seen from the second chip 120. In order to match the input resistances RI1 and RI2, the correction power supply voltage line VDD is added to be connected through a correction resistance R1 to the first chip 110.
The correction resistance R1 in the correction power supply voltage line VDD as seen from a first output terminal OUT1 of the first chip 110 is designed to be equal to the resistance RI2 in the bypass power supply voltage line VDD_bypass as seen from a first output terminal OUT1 of the second chip 120. The correction resistance R1 is expressed by Equation 2.R1=RI2=RB1+RB—i+RB2  [Equation 2]
However, the block dim effect cannot be minimized by simply matching the input resistances of the power supply voltage lines as seen from the chips. In order to minimize the block dim effect, a relationship among signals output from a plurality of the chips needs to be considered.
Referring to FIG. 1, in the conventional correction scheme, only the specific resistance of the metal line in the bypass power supply voltage line VDD_bypass from the FPC to the first chip 110, the specific resistance of the internal routing line of the first chip 110, and the specific resistance of the metal line between the first chip 110 and the second chip 120 are considered. Namely, the resistances of the power supply voltage lines as seen from the first output terminal OUT1 of the first chip 110 and the first output terminal OUT1 of the second chip 120 are to be matched.
However, the most dominant block dim effect can be observed between a 480-th output terminal OUT480 that is the last output terminal of the first chip 110 and the first output terminal OUT1 of the second chip 120 that is closest to the 480-th output terminal OUT480. Therefore, the conventional correction scheme which does not consider the fact has a problem in minimizing the block dim effect.